Intel EP80579 User Manual

Intel
®
EP80579 Integrated Processor with Intel
®
QuickAssist Technology—Technical Reference
Development Kit User’s Guide October 2008
44 Order Number: 320067-002US
4.8.9 SSP Header
The Intel
®
EP80579 Development Board provides a 2x5 header to access the
processor’s SSP I/O pins. Table 25 provides the pinout of the SSP header.
4.8.10 SIO Tertiary (Third) UART Header
The Intel
®
EP80579 Development Board utilizes the SIO to provide a third UART and
RS-232 connectivity. The UART is connected to a 2x5 header. The pinout is provided in
Table 26.
Note: SIO Tertiary UART can utilize the CAN cable interface.
4.8.11 JTAG Access Headers
The Intel
®
EP80579 Development Board provides JTAG access headers for debug
purposes. Table 27 includes the Intel
®
EP80579, PCI Express switch, and Quad
Ethernet PHY JTAG access header pinout. Table 28 lists the FPGA JTAG access header
pinout.
Table 25. SSP Header Pinout
Pin Signal Pin Signal
1NC 2SSP_SFRM
3SSP_TXD 4GND
5SSP_RXD 6GND
7SSP_CLK 8GND
9 SSP_EXTCLK 10 +3V3
Table 26. Tertiary UART Pinout
Pin Signal Pin Signal
1DCD 2 DSR
3RXD 4 RTS
5TXD 6 CTS
7DTR 8 RI
9 GND 10 NC
Table 27. Intel
®
EP80579, PEX8508 and 88E1141JTAG Header Pinout
Pin Signal Pin Signal
1TRST_N 2GND
3TDI 4GND
5TDO 6GND
7TMS 8GND
9TCK 10GND
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Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English