Status Structure 7-7
Status byte register
The summary messages from the status registers and queues are used to set or clear the appro-
priate bits (B0, B2, B3, B4, B5, and B7) of the status byte register. These summary bits do not
latch, and their states (0 or 1) are solely dependent on the summary messages (0 or 1). For exam-
ple, if the standard event register is read, its register will clear. As a result, its summary message
will reset to 0, which in turn will reset the ESB bit in the status byte register.
The bits of the status byte register are described as follows:
• Bit B0, measurement status (MSB) — Set summary bit indicates that an enabled mea-
surement event has occurred.
• Bit B1 — Not used.
• Bit B2, error available (EAV) — Set summary bit indicates that an error or status mes-
sage is present in the error queue.
• Bit B3, questionable summary bit (QSB) — Set summary bit indicates that an enabled
questionable event has occurred.
• Bit B4, message available (MAV) — Set summary bit indicates that a response message
is present in the output queue.
• Bit B5, event summary bit (ESB) — Set summary bit indicates that an enabled stan-
dard event has occurred.
• Bit B6, request service (rqs)/master summary status (MSS) — Set bit indicates that
an enabled summary bit of the status byte register is set.
• Bit B7, operation summary (OSB) — Set summary bit indicates that an enabled oper-
ation event has occurred.
Depending on how it is used, Bit B6 of the status byte register is either the request for service
(RQS) bit or the master summary status (MSS) bit:
• When using the serial poll sequence of the power supply to obtain the status byte (a.k.a.
serial poll byte), B6 is the RQS bit. See “Serial Polling and SRQ” for details on using
the serial poll sequence.
• When using the *STB? command (see Table 7-3) to read the status byte, B6 is the MSS
bit.
Service request enable register
The generation of a service request is controlled by the service request enable register. This
register is programmed by the user and is used to enable or disable the setting of bit B6 (RQS/
MSS) by the status summary message bits (B0, B2, B3, B4, B5, and B7) of the status byte reg-
ister. As shown in Figure 7-3, the summary bits are logically ANDed (&) with the corresponding
enable bits of the service request enable register. When a set (1) summary bit is ANDed with an
enabled (1) bit of the enable register, the logic “1” output is applied to the input of the OR gate
and, therefore, sets the MSS/RQS bit in the status byte register.
To Next Page
Loading...
Need help?
General
