E8257D/67D, E8663D PSG Signal Generators Service Guide 139
Troubleshooting
Overall Description
Frequency Control
CW Mode
The A9 YIG Driver, A18 CPU, A7 Reference, A5 Sampler, and A6 Frac–N
establish frequency accuracy and stability. This circuitry is commonly referred
to as a phase lock loop (PLL).
In CW operation, the A18 CPU programs the A9 YIG Driver pre–tune DAC to
output a voltage that coarsely tunes the YIG oscillator to the desired
frequency. The A18 CPU also sets the A6 Frac–N VCO and the A5 Sampler
phase dividers and VCO to a frequencies such that when the A6 Frac–N, A5
Sampler signal, and the YIG oscillator signals are in phase, the output of the
phase comparator is 0 volts, and the phase lock loop is at the desired output
frequency. When the phases of these two signals (YO feedback and reference)
are not the same (in phase), the output of the phase detector changes to some
voltage other than 0 volts.
The phase detector output is then integrated (the integrator voltage is
proportional to the frequency error), and routed to the A9 YIG Driver where it is
summed with the pre–tune DAC voltage, causing the YIG’s output frequency to
change. Once the phase of the two signals matches, the phase detector output
voltage returns to 0 volts, and the integrator maintains a constant output
voltage, holding the YIG output frequency constant.
To perform a phase comparison between the A6 Reference signal and the RF
signal coupled off by the A20 Doubler, a sampling function on the A5 Sampler
converts the RF (in GHz) to an IF frequency in the MHz range. A 10 MHz signal
from the A7 Reference Assembly is used as the reference to the A6 Frac–N
VCO (Voltage Controlled Oscillator) to maintain the A6 Frac–N frequency
accuracy. The frequency reference for the A7 Reference can be an:
— external 10 MHz signal
— internal standard 10 MHz OCXO (Oven Controlled Crystal Oscillator) on the
A7 Reference
— optional high–stability 10 MHz OCXO
In summary:
— The A18 CPU coarse tunes the YIG, and sets the A5 Sampler VCO frequency
and the A6 Frac–N VCO frequencies.
— The A5 Sampler and A6 Frac–N VCO frequencies are not fixed, and vary
according to the YIG frequency.
— In some modes, the A6 Frac–N’s VCO is divided on the A5 Sampler.
— The A5 Sampler converts the RF signal to an IF signal for phase
comparison.
— After a phase detector determines the phase difference between the two
signals, the phase detector output is integrated. The integrated voltage is
summed with the A9 YIG Driver pre–tune DAC voltage, causing the YIG
oscillator output frequency to change to the desired frequency.
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