Lime Microsystems LMS7002MR3 - Page 19

15
Address (15 bits)
Bits
Description
0x002A
15 – 14
13 – 12
11 – 10
9 – 8
7 – 6
4 – 5
3 – 2
1 – 0
FCLK2_DLY[1:0]: FCLK2 clock internal delay.
11 – 3x delay
10 – 2x delay
01 – 1x delay
00 – No delay (default)
FCLK1_DLY[1:0]: FCLK2 clock internal delay.
11 – 3x delay
10 – 2x delay
01 – 1x delay
00 – No delay (default)
RX_MUX[1:0]: RxFIFO data source selection.
00 – RxTSPCLK (default)
01 – TxFIFO
10, 11 – LFSR
TX_MUX[1:0]: Port selection for data transmit to TSP.
10, 11 – Data source is RxTSP
01 – Data source is Port 2
00 – Data source is Port 1 (default)
TXRDCLK_MUX[1:0]: TX FIFO read clock selection.
10, 11 – Clock source is TxTSPCLK (default)
01 – Clock source is FCLK2
00 – Clock source is FCLK1
TXWRCLK_MUX[1:0]: TX FIFO write clock selection.
10, 11 – Clock source is RxTSPCLK (use for TSP loop back)
01 – Clock source is FCLK2
00 – Clock source is FCLK1 (default)
RXRDCLK_MUX[1:0]: RX FIFO read clock selection.
11 – Clock source is FCLK2
10 – Clock source is FCLK1
01 – Clock source is MCLK2 (default)
00 – Clock source is MCLK1
RXWRCLK_MUX[1:0]: RX FIFO write clock selection.
10, 11 – Clock source is RxTSPCLK (default)
01 – Clock source is FCLK2
00 – Clock source is FCLK1
Default: 00000000 10000110