Lime Microsystems LMS7002MR3 - Page 20

16
Address (15 bits)
Bits
Description
0x002B
15
14
13 – 12
11 – 10
9
8
7 – 6
5 – 4
3 – 2
1
0
FCLK2_INV: FCLK2 clock inversion.
1 – Inverted
0 – Not inverted (default)
FCLK1_INV: FCLK1 clock inversion.
1 – Inverted
0 – Not inverted (default)
MCLK2_DLY[1:0]: MCLK2 clock internal delay.
11 – 3x delay
10 – 2x delay
01 – 1x delay
00 – No delay (default)
MCLK1_DLY[1:0]: MCLK2 clock internal delay.
11 – 3x delay
10 – 2x delay
01 – 1x delay
00 – No delay (default)
MCLK2_INV: MCLK2 clock inversion.
1 – Inverted
0 – Not inverted (default)
MCLK1_INV: MCLK1 clock inversion.
1 – Inverted
0 – Not inverted (default)
Reserved
MCLK2_SRC[1:0]: MCLK2 clock source.
11 – RxTSPCLKA
10 – TxTSPCLKA
01 – RxTSPCLKA after divider (default)
00 – TxTSPCLKA after divider
MCLK1_SRC[1:0]: MCLK1 clock source.
11 – RxTSPCLKA
10 – TxTSPCLKA
01 – RxTSPCLKA after divider
00 – TxTSPCLKA after divider (default)
TXDIVEN: TX clock divider enable.
1 – Divider enabled
0 – Divider disabled (default)
RXDIVEN: RX clock divider enable.
1 – Divider enabled
0 – Divider disabled (default)
Default: 00000000 00010000
0x002C
15 – 8
7 – 0
TXTSPCLKA_DIV[7:0]: TxTSP clock divider, used to produce MCLK(1/2) clocks.
Clock division ratio is 2(TXTSPCLKA_DIV + 1). Unsigned integer.
Possible values are 0 – 255, default is 255.
RXTSPCLKA_DIV[7:0]: RxTSP clock divider, used to produce MCLK(1/2) clocks.
Clock division ratio is 2(TXTSPCLKA_DIV + 1). Unsigned integer.
Possible values are 0 – 255, default is 255.
Default: 11111111 11111111
0x002D
15 – 0
Reserved
Default: 11111111 11111111
0x002E
15
14 – 0
MIMO/SISO: MIMO channel B enable control.
1 – Disables MIMO channel B, when SISO_ID (from pad) is 1.
0 – Enables MIMO channel B, when SISO_ID (from pad) is 0.
Reserved
Default: 00000000 00000000
0x002F
15 – 7
10 – 6
5 – 0
VER[4:0]: Chip version. Read only.
00111 – Chip version is 7
REV[4:0]: Chip revision. Read only.
00001 – Chip revision is 1
MASK[5:0]: Chip mask. Read only.
000001 – Chip mask is 1
Default: 00111000 01000001 (Read only)