Lime Microsystems LMS7002MR3 - Page 58

54
Address (15 bits)
Bits
Description
0x0095
15
14
13
12
11
10
9
8
7
6 – 3
2
1
0
BYP_LDO_TBB: Bypass signal for the LDO
0 – Does not bypass. Normal LDO operation (default)
1 – Bypasses LDO. Connects Vinput to Voutput
BYP_LDO_TIA12: Bypass signal for the LDO
0 – Does not bypass. Normal LDO operation (default)
1 – Bypasses LDO. Connects Vinput to Voutput
BYP_LDO_TIA14: Bypass signal for the LDO
0 – Does not bypass. Normal LDO operation (default)
1 – Bypasses LDO. Connects Vinput to Voutput
BYP_LDO_TLOB: Bypass signal for the LDO
0 – Does not bypass. Normal LDO operation (default)
1 – Bypasses LDO. Connects Vinput to Voutput
BYP_LDO_TPAD: Bypass signal for the LDO
0 – Does not bypass. Normal LDO operation (default)
1 – Bypasses LDO. Connects Vinput to Voutput
BYP_LDO_TXBUF: Bypass signal for the LDO
0 – Does not bypass. Normal LDO operation (default)
1 – Bypasses LDO. Connects Vinput to Voutput
BYP_LDO_VCOGN: Bypass signal for the LDO
0 – Does not bypass. Normal LDO operation (default)
1 – Bypasses LDO. Connects Vinput to Voutput
BYP_LDO_VCOSXR: Bypass signal for the LDO
0 – Does not bypass. Normal LDO operation (default)
1 – Bypasses LDO. Connects Vinput to Voutput
BYP_LDO_VCOSXT: Bypass signal for the LDO
0 – Does not bypass. Normal LDO operation (default)
1 – Bypasses LDO. Connects Vinput to Voutput
Reserved
EN_LOADIMP_LDO_AFE: Enables the load dependent bias to optimize the load
regulation
0 – Constant bias (default)
1 – Load dependent bias
EN_LOADIMP_LDO_CPGN: Enables the load dependent bias to optimize the load
regulation
0 – Constant bias (default)
1 – Load dependent bias
EN_LOADIMP_LDO_CPSXR: Enables the load dependent bias to optimize the load
regulation
0 – Constant bias (default)
1 – Load dependent bias
Default: 00000000 00000000