ISINK_SPIBUFF[2:0]: Controls the SPIBUF LDO output resistive load.
0 – Off (default);
1 – 10kΩ;
2 – 2.5kΩ;
3 – 2kΩ;
4 – 625Ω;
5 – 588Ω
6 – 500Ω
7 – 476Ω
SPDUP_LDO_SPIBUF: Short the noise filter resistor to speed up the settling time
0 – Noise filter resistor in place (default)
1 – Noise filter resistor bypassed
should be connected to a 1~5uS at the power up
SPDUP_LDO_DIGIp2: Short the noise filter resistor to speed up the settling time
0 – Noise filter resistor in place (default)
1 – Noise filter resistor bypassed
should be connected to a 1~5uS at the power up
SPDUP_LDO_DIGIp1: Short the noise filter resistor to speed up the settling time
0 – Noise filter resistor in place (default)
1 – Noise filter resistor bypassed
should be connected to a 1~5uS at the power up
BYP_LDO_SPIBUF: Bypass signal for the LDO
0 – Does not bypass. Normal LDO operation (default)
1 – Bypasses LDO. Connects Vinput to Voutput
BYP_LDO_DIGIp2: Bypass signal for the LDO
0 – Does not bypass. Normal LDO operation (default)
1 – Bypasses LDO. Connects Vinput to Voutput
BYP_LDO_DIGIp1: Bypass signal for the LDO
0 – Does not bypass. Normal LDO operation (default)
1 – Bypasses LDO. Connects Vinput to Voutput
EN_LOADIMP_LDO_SPIBUF: Enables the load dependent bias to optimize the load
regulation
0 – Constant bias (default)
1 – Load depdent bias
EN_LOADIMP_LDO_DIGIp2: Enables the load dependent bias to optimize the load
regulation
0 – Constant bias (default)
1 – Load depdent bias
EN_LOADIMP_LDO_DIGIp1: Enables the load dependent bias to optimize the load
regulation
0 – Constant bias (default)
1 – Load depdent bias
PD_LDO_SPIBUF: Enables the LDO
0 – Block active (default)
1 – Power down
PD_LDO_DIGIp2: Enables the LDO
0 – Block active (default)
1 – Power down
PD_LDO_DIGIp1: Enables the LDO
0 – Block active (default)
1 – Power down
EN_G_LDOP: Enable control for all the LDO power downs
0 – All LDO modules powered down
1 – All LDO modules controlled by individual power down registers
(default)
Default: 00000000 00000001
To Next Page
Loading...