C-2 Description of Self-test Test Items
Perform read and write tests for entire space of four types of DDRs that DSP FPGA
plugs in. The program displays the test results of DSP buffer DDR (transmitting DSP
processing result data), SCAN buffer DDR (transmitting scan control frame), IQ buffer
DDR (transmitting IQ data) and Gather buffer DDR (collecting data).
Analysis to test failure
The drive goes wrong if the test result appears Error.
The connection error between FPGA and plug-in DDR occurs if the test result is FAIL.
Suggestion to test failure
a) Restart the device and perform the self-test if the test result appears Error. It is
necessary to restore the device if Error re-appears.
b) It is recommended to replace CPU if the test result is FAIL.
C.1.4 Z0203 DSP FPGA and TRA Interconnection Test
(Control Interface)
Top test items
PC Module and DSP FPGA Interconnection Test
Test content
Test whether the control bus communication between DSP FPGA and XCVER of TRA
FPGA works well via reading the register.
Analysis to test failure
The drive goes wrong if the test result appears Error.
The connection error between DSP FPGA and TRA FPGA occurs if the test result is
FAIL.
Suggestion to test failure
a) Restart the device and perform the self-test if the test result appears Error. It is
necessary to restore the device if Error re-appears.
b) It is recommended to change CPU if the test result is FAIL.
C.1.5 Z0204 TRA AFE SPI Interface Test
Top test items
DSP FPGA and TRA Interconnection Test (Control Interface)
Test content
Test whether the SPI control bus communication between TRA FPGA and AFE works
well via reading the registering.
Analysis to test failure
The drive goes wrong if the test result appears Error.
TRA FPGA and AFE’s SPI bus have communication error if the test result is FAIL.
Suggestion to failure test
a) Restart the device and perform the self-test if the test result appears Error. It is
necessary to restore the device if Error re-appears.
b) It is recommended to change CPU if the test result is FAIL.