Memory Map
20 MIPS® Malta™ User’s Manual, Revision 01.07
Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
NOTE: The initial value for WIDTH of 10 ms will cause problems, if the baud rate of the tty0 port is less than 2400
Baud. If baud rates below 2400 Baud are used, this register must be programmed with a larger value.
3.7 CBUS UART, tty2
For details on programming the CBUS UART (TI 16C550C), see the data sheet from Texas Instruments [10]. The
clock frequency for baud rate calculations is 3.6864 MHz.
The UART registers of the UART are 8 bits wide and mapped on 64-bit aligned boundaries. These registers are
described in Table 3.15.
3.8 General Purpose I/O
The Malta Board has eight GP inputs and eight GP outputs connected to the Core Board. For usage details, refer to
the documentation on the specific Core Board.
Reset Value: 0x0A
Table 3.14 BRKRES Register
Bits Field Name Function Initial Value
31:8 Reserved Reserved 0
7:0 WIDTH Writing a value to this address indicates the
number of milliseconds in length a “Break”
must be on the tty0 port in order to trigger a
reset. Valid values are from 0 to 255.
A value of zero prevents this reset ever occur-
ring.
0x0A
(i.e., 10ms)
Table 3.15 UART Registers. BASE = 0x1F00.0900
Name Offset Address Access Function
RXTX 0x0000.0000 R/W Receive / Transmit char register
INTEN 0x0000.0008 R/W Interrupt enable register
IIFIFO 0x0000.0010 R/W Read: Interrupt identification
Write: FIFO control
LCTRL 0x0000.0018 R/W
Line control register
1
1. The Divisor Latch Registers are accessible through RXTX and INTEN registers when bit 7
(Divisor Latch Access Bit) of the Line Control Register is set.
MCTRL 0x0000.0020 R/W Modem control register
LSTAT 0x0000.0028 R/W Line status register
MSTAT 0x0000.0030 R/W Modem status register
SCRATCH 0x0000.0038 R/W Scratch register
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