Chapter 7
MIPS® Malta™ User’s Manual, Revision 01.07 49
Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
Core Card Design
This chapter describes the external specification with which all Core cards must comply.
7.1 Required Interfaces
This section describes the interfaces that must be present on the Core card.
7.1.1 Power
Power supplies at 3.3V, 5V and 12V, positioned such that if a Core card is placed on the motherboard 180 degrees
incorrectly, all rails are shorted out by a number of pins. This should place the PSU in shutdown mode.
It is not guaranteed that the 5V rail will be present before the 3.3V rail.
7.1.2 PCI Bus
The interface to the core card includes a PCI bus. All core cards shall be 5V tolerant on inputs but drive 3.3V on all
outputs on the PCI bus.
7.1.3 Clock
The PCI bus clock is driven to the Core card from the motherboard. The Core card shall be able to run with this clock
at any frequency from 0-33MHz.
7.1.4 Revision Number
The Core card drives a processor-readable revision number, via pins CREV[7:0], down to the motherboard where the
CPU will be able to read them via the CBUS.
This revision number could for example be set via 8 fit/not-fit resistors.
7.1.5 I
2
C bus
An I
2
C bus is present on the interface. This will typically be used for interrogating SDRAM DIMMs. See User Man-
ual for the address map.
7.1.6 Interrupts
Six interrupt signals to the MIPS CPU on the Core card are present, as is a single NMI interrupt signal, triggered by a
front-panel push button. Core cards must route all of these interrupts to the CPU—if the CPU chip has fewer external
interrupt pins, they should be ORed together.
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