Mips Technologies Malta - Signals; Table 7.2 Core Card Interface Signals

Core Card Design
52 MIPS® Malta™ User’s Manual, Revision 01.07
Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
7.2 Signals
The Core card interface signals are carried on J3 and J4, which are 200-pin (4-row) 1.27mm pitch connectors,
SAMTEC type MOLC-150-31-S-Q (male, fitted to Core card). The interface signals are described in Table 7.2.
Table 7.2 Core Card Interface Signals
Signal
Direction (from
Core Card)
Pull (on Core
Card)
Pull (on
Motherboard) Description
INTN[5:0] Input up - Interrupt signals to CPU.
NMIN Input up - NMI signal to CPU
CD[31:0] I/O - - CBUS data bus
CCSN Output - - CBUS chip select
CA[25:2] Output - - CBUS Address
CRDN Output - - CBUS read strobe
CWRN Output - - CBUS write strobe
SCK I/O - - IIC bus clock
SDA I/O - - IIC bus data
CINTHIN Output - up Core card interrupt signal down to the moth-
erboard (high priority).
CINTLON Output - up Core card interrupt signal down to the moth-
erboard (low priority).
CREV[7:0] Output - - Indicates Core card revision as a 6.2 bit
binary number
BIGEND Input - - Sets CPU Endianness.
EJTCK Input - down
EJTMS Input - up
EJTRSTN Input - down
EJTDI Input - up
EJTDO Output - -
EJDINT Input - down
JTGCPU Input - down Sets Core card’s JTAG output to come direct
from the CPU rather than also via other cir-
cuits.
CGPI[7:0] Output - - General purpose output from Core which can
be read from the motherboard.
CGPO[7:0] Input - - General purpose input to Core which the
motherboard can drive.
CUU[15:0] - - - Unused pins, connected to wire-wrap area on
both Core and the motherboard.
CPRESN Output strong
down
up Wired to zero, to indicate presence of Core
card.
APRESN Input up strong
down
Wired to zero on the motherboard, to indicate
attachment.
D12V Input - - Twelve volt power for possible fan