Mips Technologies Malta - Reset; Clocks; Interrupt Controller

5.4 Reset
MIPS® Malta™ User’s Manual, Revision 01.07 33
Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
5.4 Reset
A push-button switch (S3) is provided to reset the board. Alternative sources of reset are:
• the CBUS FPGA, when a “magic” value is written to the SOFTRES register
• the EJTAG probe system reset signal (EJRSTN)
• an incoming break on the tty0 port (J6). This break may be disabled by software.
All resets are the same - there is no difference between a “warm” and a “cold” reset. All hardware, including hard-
ware driven by stand-by voltages, are reset at reset.
5.5 Clocks
The PCI clock normally runs at 33 MHz, generated from a 14.31818 MHz crystal using a clock synthesizer/driver
(U13). The PCI clock can be configured via JP4 (see Table 4.1).
This will not affect the clock frequency of a CPU mounted on its Core Board; the Core Board generates its own clock.
The Malta Board contains the following clocks:
• RTC (32.768 KHz)
• CBUS UART (tty2) (3.6864 MHz)
• ISA Environment (14.31818 MHz)
• Ethernet (25 MHz)
• PCI clock (33 MHz - configurable to 10, 12.5, 16.67, 20, 25, 30, 33.33 and 37.5 MHz)
• CBUS FPGA (40 MHz)
• USB (48 MHz)
5.6 Interrupt Controller
The interrupt controller is located in the South Bridge device. An NMI interrupt controller (for South bridge NMI and
ON/NMI button) is located in the FPGA (see Section 3.2, "NMI Interrupts").
Interrupts routed to the South Bridge are triggered by the following devices:
• South Bridge internal devices (timer, real time clock, USB)
• Super I/O devices (keyboard, 2 UARTs, floppy disk, parallel port, mouse)
• Ethernet controller
• Audio controller