Mips Technologies Malta - Page 34

Hardware Description
34 MIPS® Malta™ User’s Manual, Revision 01.07
Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
• Primary and Secondary IDE devices
• PCI slots 1..4
• SERR (PCI bus) and IOCHK (ISA bus) signals may trigger the South Bridge NMI interrupt
• Various power management related events in the South Bridge may trigger the South Bridge SMI interrupt
•I
2
C bus controller in the South Bridge may trigger either the South bridge SMI or IRQ9 interrupt
Interrupts routed directly to the Core Card are triggered by the following devices :
• Core card (COREHI, CORELO signals)
• Discrete 16550 UART device (CBUS UART (tty2))
Figure 5.2 shows the interrupt wiring. The figure does not include the connections of SERR from the PCI slots and
the Core Card to the South Bridge.
IRQ 0..15 from devices located in the Super I/O device are routed to the South Bridge using a serial connection.
PCI A..D interrupts including the South Bridge USB controller (using PCI D) are mapped on IRQ 0..15, which are
further multiplexed to South Bridge INTR.
Based on the interrupt sources, the South Bridge generates 3 interrupts : INTR, SMI, and NMI.