Mips Technologies Malta - Page 4

4 MIPS® Malta™ User’s Manual, Revision 01.07
Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
5.17.1: Software Debug ............................................................................................................................. 40
5.17.2: Hardware Debug............................................................................................................................ 40
Chapter 6: 1284 Flash Download Format ...........................................................................................45
Chapter 7: Core Card Design...............................................................................................................49
7.1: Required Interfaces ................................................................................................................................... 49
7.1.1: Power............................................................................................................................................... 49
7.1.2: PCI Bus............................................................................................................................................ 49
7.1.3: Clock ................................................................................................................................................ 49
7.1.4: Revision Number.............................................................................................................................. 49
7.1.5: I2C bus............................................................................................................................................. 49
7.1.6: Interrupts.......................................................................................................................................... 49
7.1.7: Endian.............................................................................................................................................. 50
7.1.8: CBUS ............................................................................................................................................... 50
7.1.9: EJTAG.............................................................................................................................................. 51
7.1.10: Misc................................................................................................................................................ 51
7.2: Signals....................................................................................................................................................... 52
7.2.1: J3 Connector.................................................................................................................................... 53
7.2.2: J4 Connector.................................................................................................................................... 55
7.3: Physical Design......................................................................................................................................... 56