Mips Technologies Malta - Page 6

6 MIPS® Malta™ User’s Manual, Revision 01.07
Copyright © 2000-2007 MIPS Technologies Inc. All rights reserved.
List of Tables
Table 3.1: Malta Physical Memory Map.................................................................................................................. 13
Table 3.2: I2C Slave Address Map ......................................................................................................................... 14
Table 3.3: REVISION Register ............................................................................................................................... 14
Table 3.4: NMISTATUS Register............................................................................................................................ 15
Table 3.5: NMIACK Register................................................................................................................................... 16
Table 3.6: SWITCH Register................................................................................................................................... 16
Table 3.7: STATUS Register .................................................................................................................................. 16
Table 3.8: JMPRS Register .................................................................................................................................... 17
Table 3.9: Display Registers. BASE = 0x1F00.0400 .............................................................................................. 17
Table 3.10: LEDBAR Register ................................................................................................................................ 18
Table 3.11: ASCIIWORD Register.......................................................................................................................... 19
Table 3.12: ASCIIPOS0-7 Registers....................................................................................................................... 19
Table 3.13: SOFTRES Register.............................................................................................................................. 19
Table 3.14: BRKRES Register................................................................................................................................ 20
Table 3.15: UART Registers. BASE = 0x1F00.0900 .............................................................................................. 20
Table 3.16: GPOUT Register.................................................................................................................................. 21
Table 3.17: GPINP Register ................................................................................................................................... 21
Table 3.18: I2CINP Register................................................................................................................................... 22
Table 3.19: I2COE Register.................................................................................................................................... 22
Table 3.20: I2COUT Register ................................................................................................................................. 22
Table 3.21: I2CSEL Register .................................................................................................................................. 23
Table 4.1: Interface Connectors.............................................................................................................................. 26
Table 4.2: Jumpers ................................................................................................................................................. 27
Table 4.3: Switches................................................................................................................................................. 28
Table 4.4: LEDs ...................................................................................................................................................... 29
Table 4.5: Ethernet Connector LED Functionality................................................................................................... 30
Table 5.1: IDSEL and INT# for PCI Devices........................................................................................................... 31
Table 5.2: IRQ 0..15 Mapping................................................................................................................................. 36
Table 5.3: CPU INT0..5 and CPU NMI Mapping..................................................................................................... 36
Table 5.4: Serial Port Pinouts ................................................................................................................................. 37
Table 5.5: Testpoints .............................................................................................................................................. 40
Table 5.6: Logic Analyser Connectors.................................................................................................................... 41
Table 6.1: Download Codes.................................................................................................................................... 46
Table 6.2: Flash Download Error Messages........................................................................................................... 46
Table 7.1: CBUS AC Timing Parameters................................................................................................................ 51
Table 7.2: Core Card Interface Signals................................................................................................................... 52
Table 7.3: J3 Pin List .............................................................................................................................................. 53
Table 7.4: J4 Pin List .............................................................................................................................................. 55
Table 7.5: Core Card Component Height Restrictions............................................................................................ 57