9 CREATING A HARDWARE LOGIC
9.1 Main Blocks in the Hardware Logic Outline Window
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Output
The following table shows the outputs of the SSI encoder block.
*1 The "Absolute Encoder" terminal of a 32-bit unsigned multi function counter block can be linked.
The refreshing cycle of a count value is calculated by the following formula because the module processing
time fluctuates within the range of 0 to 100μs.
Refreshing cycle = (Data frame length + P + 1) × Clock cycle + Monoflop time + Module processing time (0 to
100μs)
• P: 1 (for with parity) or 0 (for without parity)
• Clock cycle: Inverse of the transmission speed (for the transmission speed of 100kHz: 1/100000s = 10μs)
Note that if an SI device terminal is used, up to 200μs may be added to the refreshing cycle above as a delay
time of the refreshing.
Variable name Data type Linkable block Output value Description
Clock Bit External output 0, 1 Outputs the clock signal to perform synchronous data
communication with the SSI encoder.
When an SSI encoder block is arranged in the
hardware logic outline window, the "Clock" terminal of
the SSI encoder block and the "Input" terminal of an
external output block are automatically linked. The link
cannot be deleted or changed.
The following are the link destinations.
• Serial_Encoder0: OUT 0_DIF
• Serial_Encoder1: OUT 1_DIF
Output Word Multi function counter
*1
0 to 4294967295 Sets the position data acquired from the SSI encoder to
a count value of the multi function counter block linked.
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