9 CREATING A HARDWARE LOGIC
9.1 Main Blocks in the Hardware Logic Outline Window
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9
■Single turn
The following example is for the receive frame of a single turn encoder. The receive frame consists of the elements below.
• Single turn: 24 bits
• Status bit: 1 bit
• Parity bit: None
• Parameter
*1 For details on the encoder specifications, refer to the manual for the encoder used.
• Parameters of "Data Frame Setting"
*2 For details on the encoder specifications, refer to the manual for the encoder used.
Encoder specifications
*1
SSI encoder block setting Remarks
Item Setting value
Encoder type Single turn Encoder Type Single Turn
Transmission speed 2MHz Transmission Speed 2.0MHz
Monoflop time 10μs Monoflop Time 10
Signal Error Detection Disable Set "Enable" to use the signal error detection.
Set "Disable" not to use it.
Direction Reverse Set "Forward" to count a position data from the
SSI encoder in the forward direction. Set
"Reverse" to reverse the counting direction.
Encoder specifications
*2
SSI encoder block setting Remarks
Item Setting value
Data type Pure binary Input Data Type Pure binary
Data frame length 27 bits Data Frame Length 27
Multi turn data length Multi Turn Data Length 0 Setting is not required.
Multi turn data start bit
position
Multi Turn Start Bit 0 Setting is not required.
Encoder resolution 16777216 Encoder Resolution 0 Changing the setting value from the initial value
(0) is not required because the single turn data
length is 24 bits and the encoder resolution is
16777216 (= 2
24
).
Single turn data length 24 bits Single Turn Data Length 24
Single turn data start bit
position
0 Single Turn Start Bit 0 Specify the receive frame bit position where
single turn data starts.
Parity check Parity None
01234567891011121314151617181920212223242526
S13S14S15S16S17S18S19S20S21S22S23 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 S00
Clock
DATA
Single turn start bit position
Receive frame
bit position
Most
significant bit
Least significant bit
Single turn: 24 bits
Data frame length: 27 bits
Status bit: 1 bit