May 25, 2005 6881096C74-B
3-40 Theory of Operation: Transmitter
Figure 3-31. Power Control Components (UHF Range 2)
Power Control Loop
VFORWARD from the ON is buffered via the non-inverting, variable-gain stage U0956-2 whose gain
is set by EPOT U0952. The proper gain is determined during power-detection calibration tuning.
Buffered VFORWARD (U0956-2, Pin 7) is added to PWR_SET via R0971 and R0972 and then
compared to a reference determined by R0974 and R0975. PWR_SET is supplied by the digital-to-
analog converter (DAC) U0959, Pin 2. Comparator stage U0956-3 increases or decreases
RFPA_CNTRL so that the voltage at U0956-3, Pin 9 in the same at the reference voltage at U0956-
3, Pin 10. When the PWR_SET voltage is decreased, U0956-3 increases RFPA_CNTRL to increase
VFORWARD which is proportional to forward power thus increasing the power level. When the
PWR_SET voltage is increased, U0956-3 decreases RFPA_CNTRL to decrease VFORWARD, thus
decreasing the power level. The microprocessor initiates the loop through U0958-1 and Q0954.
Loop timing is set via software together with R0977 and C0973.
EEPOT
U0952
Q0954
RFPA_CNTRL
(TO RFPA)
U0957-4
U0957-4
U0956-3
Q0955
TEMP_2
(U0959, PIN 10)
VTEMP
(FROM RFPA)
PA_EN
CURR_LIM_SET
(U0959, PIN1)
VCURRENT
(FROM RFPA)
9.3V
9.3V
9.3V
9.3V
9.3V
9.3V
9.3V
VFORWARD
(FROM ON)
PWR_SET
(U0959, PIN 2)
D0950
D0951
1.5V
D0952
U0957-1
U0956-2
U0957-2
TEMP_1
(U0959, PIN 9)
+
-
+
-
+
-
+
-
+
-
+
-
+
-
MAEPF-27889-O
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