Nuvoton NuEclipse - Configuration of Cortex-A, Multi-Core SMP and AMP System; Preliminary Preparation

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NuEclipse

Apr. 25, 2022 Page 41 of 57 Rev 1.02.019

ECLIPSE USER MANUAL

Configuration of Cortex-A, Multi-core SMP and AMP system

4.10.1 Preliminary Preparation

Suggest using Nu-Link2 family as debugger, and being sure to upgrade Nu-Link2 firmware version

higher than v3.09.7380r.

The term SMP stands for symmetric mulitiprocessing, AMP is asymmetric mulitiprocessing.

Nu-Link2 had built-in CMSIS-DAP interface from v3.09.7380r, and this CMSIS-DAP interface is used to

support Single Cortex-A, Multi-Core SMP and AMP (Cortex-A + Cortex-M).

Besides, NuEclipse provides GNU toolchain for the Cortex-A family which resides in NuEclipse/Others

folder. After configuring this toolchain (see Section 3.1.3), we can build MA35D1’s projects.

Main Page

Table of Contents2
Overview5
Supported Chips5
Requirements6
Quick Start7
Installation7
Performing the Nueclipse Installer on Microsoft Windows7
Figure 3-1 Nueclipse Setup Wizard7
Extracting the Nueclipse Tar File on Gnu/Linux8
Figure 3-2 Install.sh Script8
Verifying the Eclipse Preferences9
Figure 3-3 Preferences for Global Tools Paths9
Figure 3-4 Preferences for Openocd Nu-Link10
Running Eclipse11
Figure 3-5 Eclipse.exe and Related Folders11
Development Tutorial12
Select Workspace12
Figure 4-1 Selecting a Workspace12
New Project Wizard13
Figure 4-2 New Project Wizard13
Figure 4-3 Target Processor Settings14
Import Existing Projects15
Figure 4-4 Importing Projects15
Build Settings16
Figure 4-5 Build Settings16
Debug Configuration17
Figure 4-6 Debug Configuration17
Debugger Tab18
Figure 4-7 Configuring the Debugger Tab18
Startup Tab19
Figure 4-8 Configuring the Startup Tab19
Debug Views20
Registers View20
Figure 4-9 Registers View20
Memory View21
Figure 4-10 Memory View21
Disassembly View22
Figure 4-11 Clicking the Instruction Stepping Mode Button22
Figure 4-12 Disassembly View22
Peripheral Registers View23
Figure 4-13 Opening the Packs Perspective23
Figure 4-14 How to Download Packages24
Figure 4-15 Locations of Repositories25
Figure 4-16 Installing SFR Files26
Figure 4-17 Device Selection27
Figure 4-18 Peripheral Registers View28
Watchpoints29
Figure 4-19 Toggle Watchpoint29
Figure 4-20 Properties for C/C++ Watchpoint30
Figure 4-21 Added Watchpoint in the Breakpoints View30
Debug in RAM31
Figure 4-22 Memory Layout31
Figure 4-23 Modifying the Ld Script32
Figure 4-24 Debug Configuration Settings33
Figure 4-25 Debugging in RAM34
Debug Executable Files Only35
Figure 4-26 Importing Executable for Debugging35
Figure 4-27 Selecting Executable36
Figure 4-28 Choosing GDB Nuvoton Nu-Link Debugging37
Figure 4-29 Locating the GDB Executable38
Figure 4-30 Choosing the ELF File to Download39
Figure 4-31 Adding Source Lookup Path40
Configuration of Cortex-A, Multi-Core SMP and AMP System41
Preliminary Preparation41
Configuration of Debugging Single-Core Cortex-A42
Figure 4-32 Configuring the Startup Tab for MA35D142
Figure 4-33 How to Disable Command Timeout43
Figure 4-34 Disable CPU1 Setting44
Figure 4-35 Configuring the Debugger Tab for Single-Core Debugging on MA35D144
Configuration of Debugging Dual-Core Cortex-A in SMP Mode45
Configuration of Debugging Single-Core Cortex-A and Cortex-M in AMP Mode45
Figure 4-36 Configuring the Debugger Tab for Multi-Core Debugging on M4 Core45
Figure 4-37 Configuring the Launch Group46
Configuration of Debugging Dual-Core Cortex-A and Cortex-M in AMP Mode47
Figure 4-38 How to Disable SMP47
Figure 4-39 Multi-Core Debugging47
Configuration of Debugging Cortex-A Core in AARCH32 Mode48
Figure 4-40 Locating the AARCH64 GDB Executable49
Figure 4-41 the First Time to Enter the Debug Mode Settings49
Figure 4-42 the Second Time to Enter the Debug Mode Settings50
Figure 4-43 AARCH32 Program Debugging50
System Registers Access51
Figure 4-44 System Register View51
Figure 4-45 Use Command to Access System Registers51
Figure 5-1 Adding Udev Rules53
Figure 5-2 Preferences for String Substitution54
Figure 5-3 more Options for Nulink255
Revision History56

Nuvoton NuEclipse - Configuration of Cortex-A, Multi-Core SMP and AMP System; Preliminary Preparation

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