Nuvoton NuEclipse - Configuration of Debugging Cortex-A Core in AARCH32 Mode

NuEclipse
Apr. 25, 2022 Page 48 of 57 Rev 1.02.019
NU
ECLIPSE USER MANUAL
4.10.6 Configuration of debugging Cortex-A Core in AARCH32 mode
The settings in chapter 4.10 are mostly for ARM v8a AARCH64 mode by default. In this section, we
describe how to debug a AARCH32 application.
For example, to debug AARCH32 program on Cortex-A35, we first enter debug mode to run AARCH64
code and leave debug mode. And then re-enter debug mode switching to AARCH32 code for debugging.
We import executable files (see Section 4.9) and create the corresponding debug configurations (see
Section 4.5). On Windows, the location where numicroMA35D1.cfg resides could be
C:\Program Files (x86)\Nuvoton Tools\OpenOCD\scripts\target. On GNU/Linux, it could be
/usr/local/OpenOCD/scripts/target. There are several steps to follow:
1. Import an executable for debugging (referring to Figure 4-26).
2. Click browse following select executable, then select an executable (referring to Figure 4-27).
3. Choose GDB Nuvoton Nu-Link Debugging as a Launch Configuration (referring to Figure
4-28).
4. Locate the GDB executable in the debug configuration (referring to Figure 4-40).
5. Choose the ELF file to download and initial setting in the debug configuration (referring to
Figure 4-41). Please based on DDR of dev-board to select the corresponding DDR initial file.
6. These files could be found in C:\Program Files (x86)\Nuvoton Tools\OpenOCD\scripts\board
folder.
7. (monitor Script ../scripts/board/numicroMA35D1_DDR3_256MB_1066MBPS_WINBOND.cfg)
8. Press on the Debug button.
9. Set breakpoint at the last address of aarch64 program and resume to the address.
10. Press run button and then leave debug mode.
11. Uncheck the reset settings and re-enter debug mode (referring to Figure 4-42).
12. Debug AARCH32 program (referring to Figure 4-43).
The above description is for debugging AARCH32 program in dual core SMP mode. AARCH32 program
debugging can also be used in the following two settings
1. Refer to Figure 4-34 to disable CPU1 setting for single core mode.
2. Refer to Figure 4-38 to disable the CPU SMP for AMP mode.