LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 2.1 — 9 May 2018 100 of 105
NXP Semiconductors
LPC5411x
32-bit ARM Cortex-M4/M0+ microcontroller
LPC5411x v.1.4 20160711 Product data sheet - LPC5411x v.1.3
Modifications:
• Updated Table 16 “Static characteristics: Power consumption in deep-sleep and deep
power-down modes”. Added Max values to I
DD
supply current in deep-sleep mode and deep
power-down mode.
• Updated Table 17 “Static characteristics: Power consumption in deep-sleep and deep
power-down modes”. Added Max values for deep-sleep mode and deep power-down mode.
• Updated Table 30 “Dynamic characteristics: I2S-bus interface pins [1][4]”.
• Updated Table 31 “SPI dynamic characteristics[1]”.
• Updated Table 32 “USART dynamic characteristics[1]”.
• Updated Table 5 “Termination of unused pins”. Added USB_DP and USB_DM.
• Updated USART features: Maximum bit rates of 6.25 Mbit/s in asynchronous mode and
Maximum data rate of 20 Mbit/s in synchronous master mode and 16 Mbit/s in synchronous
slave mode.See Section 7.17.4.
• Added a remark to the features of Section 7.17.5 “SPI serial I/O controller”.
• Updated SPIO features. Added maximum and minimum data rates for SPI functions in master
mode and slave mode. See Section 7.17.5.
• Updated Figure 8 “LPC5411x clock generation”.
• Added a table note to Table 16 “Static characteristics: Power consumption in deep-sleep and
deep power-down modes”: [3] Guaranteed by characterization, not tested in production. VDD =
2.0 V.
• PLL section renamed to System PLL. See Section 11.4 “System PLL”.
• Added Section 13.1 “Start-up behavior”.
• Updated Figure 31 “Standard I/O and RESET pin configuration”.
• Added Section 13.6 “Suggested USB interface solutions”.
• Added Table 39 “Temperature sensor static and dynamic characteristics”.
• Added Figure 29 “LLS fit of the temperature sensor output voltage”.
• Updated Table 30 “Dynamic characteristics: I2S-bus interface pins [1][4]”: common to input and
output, t
WH
and t
WL
typical values.
• Added a remark to the features of Section 7.17.8 “I2S-bus interface”.
• Updated Table 19 “Typical AHB/APB peripheral power consumption [3][4][5]”:
– USB, GPIO0, MAILBOX, SCTimer/PWM, PINT, RTC for: CPU: 12 MHz, sync APB bus: 12
MHz.
– GPIO0 and GINT for: CPU: 96MHz, sync APB bus: 96 MHz.
– GINT for: CPU: 48 MHz, sync APB bus: 48 MHz.
• Removed the section: Power-up ramp conditions.
• Updated Table 25 “Dynamic characteristics of the PLL[1]”:
– f
ref
changed to F
in
; reference frequency to input frequency.
– removed f
refjitter
.
• Updated Table 30 “Dynamic characteristics: I2S-bus interface pins [1][4]”
– removed rise time (t
r
) and fall time (t
f
).
Table 43. Revision history …continued
Document ID Release date Data sheet status Change notice Supersedes
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