NXP Semiconductors LPC5411 Series

LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 2.1 — 9 May 2018 71 of 105
NXP Semiconductors
LPC5411x
32-bit ARM Cortex-M4/M0+ microcontroller
[2] Clock Divider register (DIV) = 0x0.
[3] Typical ratings are not guaranteed.
[4] The Flexcomm Interface function clock frequency should not be above 48 MHz. See the data rates section
in the I
2
S chapter (UM10912) to calculate clock and sample rates.
[5] Based on simulation. Not tested in production.
Fig 20. I
2
S-bus timing (master)
Fig 21. I
2
S-bus timing (slave)
aaa-026799
I2Sx_SCK
I2Sx_TX_SDA
I2Sx_WS
T
cy(clk)
t
f
t
r
t
WH
t
WL
t
v(Q)
t
v(Q)
t
su(D)
t
h(D)
I2Sx_RX_SDA
aaa-026800
T
cy(clk)
t
f
t
r
t
WH
t
su(D)
t
h(D)
t
su(D)
t
h(D)
t
WL
I2Sx_SCK
I2Sx_RX_SDA
I2Sx_WS
I2Sx_TX_SDA
t
v(Q)