49
(in order from the top) to a LOAD NOT, an OR NOT, and an OR instruction.
Again, each of these instructions requires one line of mnemonic code.
Instruction
00100
LR 0000
00000
Address Instruction Operands
00000 LD 00000
00001 OR NOT 00100
00002 OR LR 0000
00003 Instruction
The instruction will have an ON execution condition when any one of the
three conditions is ON, i.e., when IR 00000 is OFF, when IR 00100 is OFF, or
when LR 0000 is ON.
OR and OR NOT instructions can be considered individually, each taking the
logical OR between its execution condition and the status of the OR instruc-
tion’s operand bit. If either one of these were ON, an ON execution condition
will be produced for the next instruction.
When AND and OR instructions are combined in more complicated dia-
grams, they can sometimes be considered individually, with each instruction
performing a logic operation on the execution condition and the status of the
operand bit. The following is one example. Study this example until you are
convinced that the mnemonic code follows the same logic flow as the ladder
diagram.
Instruction
00002 0000300000 00001
00200
Address Instruction Operands
00000 LD 00000
00001 AND 00001
00002 OR 00200
00003 AND 00002
00004 AND NOT 00003
00005 Instruction
Here, an AND is taken between the status of IR 00000 and that of IR 00001
to determine the execution condition for an OR with the status of IR 00200.
The result of this operation determines the execution condition for an AND
with the status of IR 00002, which in turn determines the execution condition
for an AND with the inverse (i.e., and AND NOT) of the status of IR 00003.
In more complicated diagrams, however, it is necessary to consider logic
blocks before an execution condition can be determined for the final instruc-
Combining AND and OR
Instructions
Basic Ladder Diagrams Section 4-3
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