PUMA T2
Technical Handbook
Technical description
P/N: 779-0306/01
Revision 03
OTE Proprietary information
Page 43
The DSP manages the firmware execution of:
• Physical Layer numerical processing algorithm both in uplink and downlink;
• TETRA protocol relative to the lower MAC sub-level.;
• interface from/to I/F AUDIO for the digital audio signal;
• serial interface from/to I/F RT for the base band TETRA modulated signal.
• execution cryptography algorithms (only for DSP320VC549-100 ECLIPSE)
The timebase has the following tasks:
• generation of the frame clock rate (at Timeslot recurrence frequency);
• generation of the timings tied to the voice frame;
• generation of the timing pulse for driving the various synchronous serial links
required by the base band architecture for the interfaces between the
functional blocks;
• serial conversion of the base band signals in uplink and downlink between I/F
RT and the DSP functional block;
• generation of the selections for some external peripherals (of the µP);
• integration of the microprocessor I/O gates, related to keyboard and display
control;
• integration of the keyboard decoder;
• integration of the control synchronous serial interface connected with the radio
card and the I/F RT card;
• selection of the bootstrap modality for the microcontroller during Reset;
• generation of the time base clock for the synchronous serial line in case of a
38400 and 115200 baud rate.
The PLL (Phase Locked Loop) has the following tasks:
• generation of microcontroller frequency: 9.216 MHz;
• generation of DSP frequency: 12.288 MHz (PUMA T2-400, PUMA T2-430,
PUMA T2-870), 15.36 MHz (PUMA T2-470);
• generation of Time Base frequency: 9.216 MHz.
All the above mentioned frequencies are generated by means of F
ref
coming from
the radio card.
For the integration of the I/O functions and the selection of external peripherals the
timebase exchanges signals with the microprocessor by the Address bus, Data
bus and Control bus.
To Next Page
Loading...