Pioneer PDP-5000EX - Page 177

PDP-5000EX
177
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56
7
8
C
D
F
A
B
E
CY25561SXC (FHD DIGITAL ASSY: IC3401)
• SSCG IC
Pin Arrangement (Top view)
Block Diagram
Pin Function
SSCLK
XIN/CLK
XOUT
VDD
VSS
SSCC S1 S0
Reference
Divider
Frequency
Divider
Divider
&
MUX
Input
Decoder
Logic
Modulation
Control
Loop
Filter
VCO
VDD
20k
200k
20k20k
20k
VSSVSS
VDD
XIN/CLK 1
VDD 2
VSS 3
SSCLK
XOUT
S0
S1
SSCC4
8
7
6
5
1
8
2
3
4
65 7
PD CP
No. Pin Name I/O Pin Function
1 XIN/CLK I Oscillator input/clock input
2 VDD
−
Power supply
3 VSS
−
Ground
4 SSCLK O SSCG clock output
5 SSCC I SSCG function ON/OFF input L: Disable, H: Enable
6S1IModulation frequency and band width select
7S0IModulation frequency and band width select
8 XOUT O Oscillator output