Profichip VPC3+S - Page 37

ASIC Interface 5
VPC3+S User Manual
Revision 1.04
37
Copyright © profichip GmbH, 2012
Interrupt Request Register 0, High-Byte, Address 01H (Intel):
bit 15
rw-0
FDL_Ind:
The VPC3+S has received an acyclic service request and made the data
available in an Indication-Buffer.
bit 14
rw-0
Poll_End_Ind:
The VPC3+S have send the response to an acyclic service.
bit 13
rw-0
DX_Out:
The VPC3+S have received a Data_Exchange telegram and made the new
output data available in the ‘N’ buffer.
bit 12
rw-0
Diag_Buffer_Changed:
Due to the request made by New_Diag_Cmd, the VPC3+S exchanged the
Diagnosis-Buffers and made the old buffer available to the user again.
bit 11
rw-0
New_Prm_Data:
The VPC3+S have received a Set_Prm telegram and made the data available in
the Parameter-Buffer.
bit 10
rw-0
New_Cfg_Data:
The VPC3+S have received a Chk_Cfg telegram and made the data available in
the Config-Buffer.
bit 9
rw-0
New_SSA_Data:
The VPC3+S have received a Set_Slave_Add telegram and made the data
available in the Set_Slave_Add-Buffer.
bit 8
rw-0
New_GC_Command:
The VPC3+S have received a Global_Control telegram and stored the
Control_Command in the R_GC_Command RAM cell.
Figure 5-10: Interrupt Request Register, High-Byte