Profichip VPC3+S - Page 77

PROFIBUS DP Extensions 7
VPC3+S User Manual
Revision 1.04
77
Copyright © profichip GmbH, 2012
The base address of the PLL-Buffer depends on the memory mode:
2K Byte mode: 7C0H
4K Byte mode: FC0H
Byte
Bit Position
Designation
7
6
5
4
3
2
1
0
0
reserved
In_Clock_
Detect
Out_Clock_
Detect
PLL_Synched
GC_Clock
_Error
GC_Clock_
Detect
GC_Clock_
Hit
Status
1
reserved
Enable_
In_Clock
Enable_
Out_Clock
Enable_
GC_Clock
SYNC_Mode
SYNC_Enable
PLL_Start
Command
2
:
3
1..(2
16
-1) (Default: 12)
T
PLL_W
:
PLL_Window
(Time Base
12
1
s)
4
:
5
0..(2
16
-1) (Default: 0)
T
PLL_D
:
PLL_Delay_Time
(Time Base
12
1
s)
6
:
9
1..(2
32
-1)
T
SYNC
:
SYNC_Cycle_Time
(Time Base
48
1
s)
10
:
11
reserved
Number_of_
SYNC(9:8)
Number_of_SYNC
Number_of_SYNC(7:0)
12
:
15
1..(2
32
-1)
First_Window
(Time Base
48
1
s)
16
:
17
reserved
T
PLL_I
(9:8)
T
PLL_I
:
Input_Time
(Time Base T
SYNC
)
T
PLL_I
(7:0)
18
:
19
reserved
T
PLL_O
(9:8)
T
PLL_O
:
Output_Time
(Time Base T
SYNC
)
T
PLL_O
(7:0)
20
0..255
E_limit