Profichip VPC3+S - Page 78

7 PROFIBUS DP Extensions
78
Revision 1.04
VPC3+S User Manual
Copyright © profichip GmbH, 2012
PLL Buffer
GC_Clock_Hit
r-0
GC_clock_Hit:
The VPC3+ has received a valid ‘SYNCH telegram’ during the
tolerance window.
GC_Clock_ Detect
r-0
GC_Clock_Detect:
Last SYNC signal coincides with the (expected) ‘SYNCH telegram’.
GC_Clock_Errror
r-0
GC_Clock_Error:
PLL detects Synchronization Errors and has to be resynchronized.
PLL_synched
r-0
PLL_synched:
PLL is synchronized with the DP-Masters SYNCH.
Out_Clock_Detect
r-0
Out_Clock_Detect:
Last SYNC signal coincides with the instant in time of the setpoint
transfer.
In_Clock_Detect
r-0
In_Clock_Detect:
Last SYNC signal coincides with the instant in time of the actual
value acquisition.
PLL_Start
rw-0
PLL_Start:
0 = PLL is stopped
1 = PLL is started
SYNC_Enable
rw-0
SYNC_Enable:
0 = SYNC signal is not enabled
1 = SYNC signal is send to DATAEXCH_N
SYNC_Mode
rw-0
SYNC_Mode:
0 = SYNC signal not synchronized to ‘SYNCH telegram’
1 = SYNC signal synchronized to ‘SYNCH telegram’
Enable_GC_Clock
rw-0
Enable_GC_Clock:
0 = generate no SYNC signal coincides with the (expected)
‘SYNCH telegram’
1 = generate SYNC signal coincides with the (expected)
‘SYNCH telegram’
Enable_Out_Clock
rw-0
Enable_Out_Clock:
0 = generate no SYNC signal at T
O
1 = generate SYNC signal at T
O
Enable_In_Clock
rw-0
Enable_In_Clock:
0 = generate no SYNC signal at T
I
1 = generate SYNC signal at T
I