Copyright © profichip GmbH, 2012
SDA
SCK
data line
stable;
data valid
change
of data
allowed
Figure 8-11: Bit Transfer on the I2C bus
All transactions begin with a START (S) and can be terminated by a STOP
(P) condition. A HIGH to LOW transition on the SDA line while SCK is
HIGH defines a START condition. A LOW to HIGH transition on the SDA
line while SCK is HIGH defines a STOP condition.
SDA
SCK
S
P
SDA
SCK
START condition
STOP condition
Figure 8-12: START and STOP condition
START and STOP conditions are always generated by the master. The bus
is considered to be busy after the START condition. The bus is considered
to be free again a certain time after the STOP condition.
Every byte sent on the SDA line must be 8 bits long. The number of bytes
that can be transmitted per transfer is unrestricted. Each byte has to be
followed by an Acknowledge bit. Data is transferred with the Most
Significant Bit (MSB) first.
SDA
SCK
MSB
1
2 7
8
9
1
2
3 to 8 9
Sr or P
P
Sr
S or Sr
ACK
ACK
acknowledgement
signal from slave
acknowledgement
signal from slave
START or
repeated START
condition
STOP or
repeated START
condition
byte complete,
interrupt within slave
clock line held LOW
while interrupts are serviced
Figure 8-13: Data Transfer on the I2C Bus
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