Quectel 5G Module Series Hardware Design

5G Module Series
RM500Q-AE&RM502Q-AE Hardware Design
RM500Q-AE&RM502Q-AE_Hardware_Design 35 / 86
Module
RESET#
PMIC
67
VDD 1.5V
250-600 ms
S1
TVS
R1
100k
33 pF
C1
NOTE: The capacitor C1 is recommended to be less than 47 pF.
Figure 13: Reference Circuit of RESET# with a Button
The timing of reset scenario is illustrated in the following figure.
VCC(H)
RESET#
Module Status
FCPO#(H)
RFFE_VIO_1V8
ResettingRunning Restarting
1.5 V
3.7 V
USIM1_VDD
250 ms ≤ T
RST#
≤ 600 ms
V
IH
≥ 1.19 V
1.8 V or 3.0 V
1.8 V
T
RST#-USIM
Figure 14: Reset Timing of the Module
Table 13: Reset Timing of the Module
Symbol
Min.
Typ.
Max.
Comment
T
RST#-USIM
200 ms
-
-
(U)SIM card turn-off time.
T
RST#
250 ms
400 ms
600 ms
More than 600 ms will lead to repeated module reset.

Quectel 5G Module Series Specifications

General

Brand	Quectel
Model	5G Module Series
Category	Motherboard
Language	English