Quectel 5G Module Series Hardware Design

5G Module Series
RM500Q-AE&RM502Q-AE Hardware Design
RM500Q-AE&RM502Q-AE_Hardware_Design 48 / 86
The clock and mode can be configured by AT command, and the default configuration is slave mode
using short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See
document [3] for details about AT+QDAI command.
4.5. Control and Indication Interfaces
The following table shows the pin definition of control and indication pins.
Table 20: Pin Definition of Control and Indication Interfaces
4.5.1. W_DISABLE1#
The module provides a W_DISABLE1# pin to disable or enable airplane mode through hardware
operation. W_DISABLE1# is pulled up by default. Driving it LOW will set the module to airplane mode. In
airplane mode, the RF function will be disabled.
The RF function can also be enabled or disabled through AT commands. The following table shows the
AT command and corresponding RF function status of the module.
28
PCM_SYNC
DIO, PD
PCM data frame sync
1.8 V
Pin No.
Pin Name
I/O
Description
DC Characteristics
8
W_DISABLE1#
DI, OD
Airplane mode control.
Pulled up by default.
Active LOW
1.8/3.3 V
26
W_DISABLE2#
DI, OD
GNSS disable control.
Pulled up by default.
Active LOW
1.8/3.3 V
10
WWAN_LED#
DO, OD
Indicate RF status of the module.
Open drain.
VCC
23
WAKE_ON_WAN#
DO, OD
Wake up the host.
Open drain.
1.8/3.3 V
25
DPR*
DI, PU
Dynamic power reduction.
High level by default.
1.8 V
38
SDX2AP_STATUS*
DO, PD
Status indication to AP
1.8 V
68
AP2SDX_STATUS*
DI, PD
Status indication from AP
1.8 V

Quectel 5G Module Series Specifications

General

Brand	Quectel
Model	5G Module Series
Category	Motherboard
Language	English