Quectel 5G Module Series - Appendix References; Related Documents; Terms and Abbreviations

5G Module Series
RM500Q-AE&RM502Q-AE Hardware Design
RM500Q-AE&RM502Q-AE_Hardware_Design 45 / 86
4.3.4. PCIe Timing
Figure 20: PCIe Power-up Timing of M.2 Specification
Table 17: PCIe Power-up Timing of M.2 Specification
T
FCPO#-CLKREQ#
> 90 ms
PCIE_CLKREQ#
PCIE_RST#
PCIE_REFCLK
t
power-on
t
turn-on
VCC
RESET#
Module power-on or insertion detection
FCPO#
RFFE_VIO_1V8
System turn-on and booting
V
IH
≥ 1.19 V
1.5 V
3.7 V
1.8 V
T
FCPO#-PERST#
> 100 ms
T
PERST#-CLK
> 100 μs
Figure 21: PCIe Power-up Timing of the Module
Symbol
Min.
Typ.
Max.
Comment
T
PVPGL
50 ms
-
-
Power valid to PERST# Input inactive
T
PERST#-CLK
100 μs
-
-
REFCLK stable before PERST# inactive