Quectel 5G Module Series Hardware Design

5G Module Series
RM500Q-AE&RM502Q-AE Hardware Design
RM500Q-AE&RM502Q-AE_Hardware_Design 34 / 86
3.6. Reset
RESET# is an asynchronous and active LOW signal (1.5 V logic level). Whenever this pin is active, the
module will immediately enter Power On Reset (POR) condition.
Please note that triggering the RESET# signal will lead to loss of all data in the modem and removal of
system drivers. It will also disconnect the modem from the network.
Table 12: Definition of RESET# Pin
The module can be reset by pulling down the RESET# pin for 250–600 ms. An open collector/drain driver
or a button can be used to control the RESET# pin.
Host Module
RESET#
PMIC
GPIO
67
VDD 1.5V
Reset pulse
250-600 ms
R1
100k
R3
100k
R2
1k
Q1
NPN
Figure 12: Reference Circuit of RESET# with NPN Driver Circuit
Pin No.
Pin Name
I/O
Description
DC Characteristics
Comment
67
RESET#
DI, PU
Reset the module.
Active LOW
V
IH
max = 1.575 V
V
IH
min = 1.25V
V
IL
max = 0.45V
Internally pulled up to
1.5 V with a 100 kΩ
resistor.

Quectel 5G Module Series Specifications

General

Brand	Quectel
Model	5G Module Series
Category	Motherboard
Language	English