Quectel 5G Module Series - Page 48

5G Module Series
RM500Q-AE&RM502Q-AE Hardware Design
RM500Q-AE&RM502Q-AE_Hardware_Design 47 / 86
1 2 255 256
125 μs
PCM_CLK
PCM_SYNC
MSB MSBLSB
PCM_DOUT
MSB MSBLSB
PCM_DIN
Figure 22: Primary Mode Timing
1 2 31 32
125 μs
PCM_CLK
PCM_SYNC
MSB MSB
LSB
PCM_DOUT
MSB MSB
LSB
PCM_DIN
Figure 23: Auxiliary Mode Timing
The following table shows the pin definition of PCM interface which can be applied to audio codec design.
Table 19: Pin Definition of PCM Interface
Pin No.
Pin Name
I/O
Description
DC Characteristics
20
PCM_CLK
DIO, PD
PCM data bit clock
1.8 V
22
PCM_DIN
DI, PD
PCM data input
1.8 V
24
PCM_DOUT
DO, PD
PCM data output
1.8 V