Quectel RG520N-AT - Page 11

5G Module Series
RG520N-AT_Hardware_Design 10 / 109
Figure Index
Figure 1: Functional Diagram ..................................................................................................................... 17
Figure 2: Pin Assignment (Top View) ......................................................................................................... 18
Figure 3: DRX Run Time and Current Consumption in Sleep Mode ......................................................... 32
Figure 4: Sleep Mode Application via UART .............................................................................................. 32
Figure 5: Sleep Mode Application with USB Remote Wakeup .................................................................. 33
Figure 6: Sleep Mode Application with MAIN_RI ....................................................................................... 34
Figure 7: Sleep Mode Application without Suspend Function ................................................................... 35
Figure 8: Reference Design of Power Supply ............................................................................................ 37
Figure 9: Power Supply Limits during Burst Transmission ........................................................................ 38
Figure 10: Star Structure of the Power Supply .......................................................................................... 39
Figure 11: Reference Circuit of Turning on the Module with Driving Circuit .............................................. 40
Figure 12: Reference Circuit of Turning on the Module with a Button ....................................................... 40
Figure 13: Turn-on Timing .......................................................................................................................... 41
Figure 14: Turn-off Timing .......................................................................................................................... 42
Figure 15: Reference Circuit of RESET_N with Driving Circuit ................................................................. 43
Figure 16: Reference Circuit of RESET_N with a Button .......................................................................... 43
Figure 17: Reset Timing ............................................................................................................................. 44
Figure 18: Reference Circuit of USB Application ....................................................................................... 46
Figure 19: Reference Circuit of USB_BOOT Interface .............................................................................. 48
Figure 20: Reference Circuit of (U)SIM Interface with an 8-pin (U)SIM Card Connector ......................... 49
Figure 21: Reference Circuit of (U)SIM Interface with a 6-pin (U)SIM Card Connector ........................... 50
Figure 22: Reference Circuit of I2S Application with Audio Codec ............................................................ 52
Figure 23: Primary Mode Timing ................................................................................................................ 53
Figure 24: Auxiliary Mode Timing ............................................................................................................... 53
Figure 25: Reference Circuit of SLIC PCM Interface ................................................................................. 54
Figure 26: Reference Circuit of Bluetooth PCM Interface ......................................................................... 55
Figure 27: UART Connection ..................................................................................................................... 56
Figure 28: Reference Circuit with a Voltage-level Translator..................................................................... 57
Figure 29: Reference Circuit with Transistor Circuit .................................................................................. 57
Figure 30: Reference Circuit of SDIO Interface ......................................................................................... 59
Figure 31: Reference Circuit of SPI with a Voltage-level Translator .......................................................... 62
Figure 32: PCIe Interface Connection ........................................................................................................ 63
Figure 33: Reference Circuit of the Network Status Indication .................................................................. 67
Figure 34: Reference Circuit of STATUS ................................................................................................... 67
Figure 35: Module with IPQ GPIO Application ........................................................................................... 68
Figure 36: Reference Circuit for Cellular Antenna Interfaces .................................................................... 74
Figure 37: Reference Circuit of GNSS Antenna ........................................................................................ 76
Figure 38: Microstrip Design on a 2-layer PCB ......................................................................................... 77
Figure 39: Coplanar Waveguide Design on a 2-layer PCB ....................................................................... 78
Figure 40: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) .................... 78
Figure 41: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) .................... 78