R8C/20 Group, R8C/21 Group 14. Timers
Rev.2.00 Aug 27, 2008 Page 197 of 458
REJ09B0250-0200
Figure 14.60 Operating Example of Output Compare Function
m
n
p
Value in TRDi register
m + 1 m + 1
TSTARTi bit in
TRDSTR register
1
0
TRDIOAi output
IMFA bit in
TRDSRi register
1
0
n + 1
TRDIOBi output
IMFB bit in
TRDSRi register
1
0
TRDIOCi output
IMFC bit in
TRDSRi register
1
0
Initial output “H”
“L” output by compare match
Set to “0” by a program
Count source
i = 0 or 1 m: Setting value in TRDGRAi register
n: Setting value in TRDGRBi register
p: Setting value in TRDGRCi register
The above applies to the following conditions:
The CSELi bit in the TRDSTR register is set to 1. (The TRDi register is not stopped by the compare match.)
The BFCi and BFDi bits in the TRDMR register are set to 0. (The TRDGRCi and TRDGRDi registers are not used as the buffer register.)
The EAi, EBi and ECi bits in the TRDOER1 register are set to 0. (Enable the TRDIOAi, TRDIOBi and TRDIOCi pin outputs.)
The CCLR2 to CCLR0 bits in the TRDCRi register are set to 001b. (Set the TRDi register to 000h by the compare match in the TRDGRAi register.)
The TOAi and TOBi bits in the TRDOCR register is set to 0. (initial output “L” to the compare match), the TOCi bit is set to 1. (initial output “H” to the compare match.
The IOA2 to IOA0 bits in the TRDIORAi register are set to 011b. (TRDIOAi output inversed at the TRDGRAi register compare match.)
The IOB2 to IOB0 bits in the TRDIORAi register are set to 010b. (TRDIOBi “H” output at the TRDGRBi register compare match.)
The IOC3 to IOC0 bits in the TRDIORCi register are set to 1001b. (TRDIOCi “L” output at the TRDGRCi register compare match.)
The IOD3 bit in the TRDIORCi register is set to 1. (TRDGRDi register does not control TRDIOBi pin output.)
m
n
p
n + 1
P + 1
Count
stop
Count
restarts
Output level
held
Output level
held
Output level
held
Set to 0 by a program
Set to 0 by a program
“H” output by compare match
Output inversed by compare match
Initial output “L”
Initial output “L”