Renesas R8C/20 User Manual

R8C/20 Group, R8C/21 Group 14. Timers
Rev.2.00 Aug 27, 2008 Page 216 of 458
REJ09B0250-0200
Figure 14.78 Registers TRDMR and TRDFCR in Reset Synchronous PWM Mode
Timer RD Mode Register
Symbol Address After Reset
TRDMR
0138h 00001110b
Bit Symbol Bit Name Function RW
RW
BFC1
BFD1
TRDGRD1 register function
selection bit
0 : General register
1 : Buffer register of TRDGRB1 register
TRDGRC0 register function
selection bit
0 : General register
1 : Buffer register of TRDGRA0 register
BFC0 RW
RW
TRDGRD0 register function
selection bit
0 : General register
1 : Buffer register of TRDGRB0 register
TRDGRC1 register function
selection bit
0 : General register
1 : Buffer register of TRDGRA1 register
RW
RW
—
(b3 - b1)
—
Timer RD synchronous bit Set this bit to 0 (the TRD and TRD1 registers
operate independently.) in reset synchronous
PWM mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
b7 b6 b5 b4 b3 b2
BFD0
b1 b0
0
SYNC
Timer RD Function Control Register
Symbol Address After Reset
TRDFCR
013Ah 10000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
b3 b2
OLS1
b1 b0
01
b7 b6 b5 b4
RW
CMD1 RW
Combination mode selection bit
(1,2)
Set to 01b (reset synchronous PWM
mode) in reset synchronous PWM mode.
CMD0
Normal-phase output level selection
bit (in reset synchronous PWM mode
or complementary PWM mode)
0 : Initial output “H”
Active level “L”
1 : Initial output “L”
Active level “H”
Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops).
OLS0 RW
RW
Counter-phase output level selection
bit (in reset synchronous PWM mode
or complementary PWM mode)
0 : Initial output “H”
Active level “L”
1 : Initial output “L”
Active level “H”
A/D trigger enable bit
(in complementary PWM mode)
This bit is disabled in reset synchronous
PWM mode.
RW
PWM3 RW
ADTRG
ADEG
A/D trigger edge selection bit
(in complementary PWM mode)
This bit is disabled in reset synchronous
PWM mode.
RW
PWM3 mode selection bit
(3)
This bit is disabled in reset synchronous
PWM mode.
When bits CMD1 to CMD0 are set to 01b, 10b, or 11b, the MCU enters reset synchronous PWM mode or
complementary PWM mode in spite of the setting of the TRDPMR register.
STCLK
External clock input selection bit 0 : External clock input disabled
1 : External clock input enabled
RW

Renesas R8C/20 Specifications

General

Brand	Renesas
Model	R8C/20
Category	Control Unit
Language	English