Renesas R8C/20

R8C/20 Group, R8C/21 Group 14. Timers
Rev.2.00 Aug 27, 2008 Page 263 of 458
REJ09B0250-0200
Figure 14.120 Operation in Output Compare Mode
2 cycles of maximum count source
00h
8-bit counter content
(hexadecimal number)
Count starts
Time
TSTART bit in
TRECR1 register
1
0
IR bit in
TREIC register
1
0
The above applies to the following conditions.
TOENA bit in TRECR1 register = 1 (enable clock output)
COMIE bit in TRECR2 register = 1 (enable compare match interrupt)
RCS6 to RCS5 bits in TRECSR register = 11b (compare output)
Set to 1 by a program
Set to 0 by acknowledgement of interrupt request
or a program
TREMIN register
setting value
Matched
TREO output
1
0
TCSTF bit in
TRECR1 register
1
0
Output polarity is reversed
when the compare matches
Matched
Matched