Renesas R8C/20 - Page 302

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface
Rev.2.00 Aug 27, 2008 Page 286 of 458
REJ09B0250-0200
Figure 16.3 SSCRL Register
SS Control Register L
Symbol Address After Reset
SSCRL
00B9h 01111101b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. Do not w rite to the SOL bit during the data transfer.
The data output after the serial data is output can be changed w hen w riting to the SOL bit before or after transfer.
When w riting to the SOL bit, set the SOLP bit to 0 and then w rite to bits SOLP and SOL by the MOV instruction.
SSCRH, SSCRL, SSMR, SSER, SSSR, SSMR2, SSTDR and SSRDR registers.
SOL
Serial data output value
setting bit
When read,
0 : The last bit of the serial data output is set to “L”
1 : The last bit of the serial data output is set to “H”
When w rite,
(2,3)
0 : The data outputs “L” after the serial data output
1 : The data outputs “H” after the serial data output
RW
—
(b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
—
(b7)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
—
(b3-b2)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
SOLP
SOL w rite protect bit
(2)
The output level can be changed by the SOL bit w hen
this bit is set to 0.
The SOLP bit remains unchanged even if 1 is w ritten to
it. When read, its content is 1.
RW
b7 b6 b5 b4 b3 b2 b1 b0
—
(b0)
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
SRES
Clock synchronous
serial I/O w ith chip
select control part
reset bit
When this bit is set to 1, the clock synchronous serial
I/O w ith chip select control part and SSTRSR register
are reset.
The values of the registers
(1)
in the clock synchronous
serial I/O w ith chip select register are maintained.
RW