R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface
Rev.2.00 Aug 27, 2008 Page 301 of 458
REJ09B0250-0200
Figure 16.16 Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Mode)
Start
Initialization
Dummy read on SSRDR register
Read receive data in SSRDR register
Read ORER bit in SSSR register
Last data
received?
Read RDRF bit in SSSR register
RDRF = 1 ?
No
Yes
Yes
No
No
Yes
(1)
(2)
(3)
(1) After setting each register in the clock synchronous
serial I/O with chip select register, dummy read on
the SSRDR register is performed and receive
operation is started.
(2) Determine whether the last 1-byte data is received.
When the last 1-byte data is received, set to stop
after the data is received.
(3) When a receive error occurs, perform an error
(6) process after reading the ORER bit. Then set the
ORER bit to 0. Transmit/receive can not be
restarted while the ORER bit is set to 1.
(4) Confirm that the RDRF bit is set to 1. If the RDRF
bit is set to 1, read the receive data in the SSRDR
register. If the SSRDR register is read, the RDRF
bit is automatically set to 0.
ORER = 1 ?
End
Read receive data in SSRDR register
Read ORER bit in SSSR register
Read RDRF in SSSR register
RDRF = 1 ?
No
Yes
ORER = 1 ?
SSER register RE bit ← 0
SSCRH register RSSTP bit ← 0
SSCRH register RSSTP bit ← 1
Overrun
error
process
No
Yes
(4)
(5)
(6)
(7)
(7) Confirm that the RDRF bit is set to 1. When the
receive operation is completed, set the RSSTP bit to
0 and the RE bit to 0 before reading the last 1-byte
data. If the SSRDR register is read before setting the
RE bit to 0, the receive operation is restarted again.
(5)Before the last 1-byte data is received, set the
RSSTP bit to 1 and stop after the data is
received.
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