R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface
Rev.2.00 Aug 27, 2008 Page 302 of 458
REJ09B0250-0200
16.2.5.4 Data Transmission/Reception
Data transmit/receive is a combined operation of data transmit and receive which are described before.
Transmit/receive is started by writing data in the SSTDR register.
When the 8th clock rises or the ORER bit is set to 1 (overrun error occurs) while the TDRE bit is set to 1 (data
is transferred from the SSTDR to SSTRSR registers), the transmit/receive operation is stopped.
When switching from transmit mode (TE = 1) or receive mode (RE = 1) to transmit/receive mode (Te = RE =1),
set the TE bit to 0 and RE bit to 0 before switching. After confirming that the TEND bit is set to 0 (the TDRE
bit is set to 0 when the last bit of the transmit data is transmitted), the RERF bit is set to 0 (no data in the
SSRDR register) and the ORER bit is set to 0 (no overrun error), set the TE and RE bits to 1.
Figure 16.17 shows a Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication
Mode).
When exiting transmit/receive mode after this mode is used (TE = RE = 1), a clock may be output if transmit/
receive mode is exited after reading the SSRDR register. To avoid any clock outputs, perform either of the
following:
• First set the RE bit to 0, and then set the TE bit to 0.
• Set bits TE and RE at the same time.
When subsequently switching to receive mode (TE = 0 and RE = 1), first set the SRES bit to 1, and set this bit
to 0 to reset the clock synchronous serial interface control unit and the SSTRSR register. Then, set the RE bit to
1.
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