R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface
Rev.2.00 Aug 27, 2008 Page 303 of 458
REJ09B0250-0200
Figure 16.17 Sample Flowchart of Data Transmission/Reception (Clock Synchronous
Communication Mode)
Start
Initialization
Read TDRE bit in SSSR register
SSSR register TEND bit ← 0
(1)
End
TDRE=1 ?
Write transmit data to SSTDR register
Data transmit
continued?
No
Yes
Yes
No
SSER register RE bit ← 0
TE bit
← 0
(1)
(2)
(3)
(1) After reading the SSSR register and confirming
that the TDRE bit is set to 1, write the transmit
data in the SSTDR register. When writing the
transmit data to the SSTDR register, the TDRE bit
is automatically set to 0.
(5) Set the TEND bit to 0 and
(6) the RE and TE bits in the SSER register to 0 before
ending transmit/receive mode.
Read receive data in SSRDR register
Read RDRF bit in SSSR register
RDRF=1 ?
No
Yes
(4)
(2) Confirm that the RDRF bit is set to 1. If the RDRF
bit is set to 1, read the receive data in the SSRDR
register. When reading the SSRDR register, the
RDRF bit is automatically set to 0.
(3) Determine whether the transmit data is continued.
(5)
NOTE:
1. Write 0 after reading 1 to set the TEND bit to 0.
Read TEND bit in SSSR register
TEND=1 ?
Yes
No
(6)
(4) When the data transmit is completed, the TEND
bit in the SSSR register is set to 1.
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