R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface
Rev.2.00 Aug 27, 2008 Page 324 of 458
REJ09B0250-0200
16.3.3 I
2
C Bus Interface Mode
16.3.3.1 I
2
C Bus Format
Setting the FS bit in the SAR register to 0 communicates in I
2
C bus format.
Figure 16.32 shows the I
2
C Bus Format and Bus Timing. The 1st frame following start condition consists of 8
bits.
Figure 16.32 I
2
C Bus Format and Bus Timing
SDA
SCL
S
SLA R/W A DATA A DATA A P
1 to 7 8 9 1 to 7 8 9 1 to 7 8 9
(2) I
2
C bus timing
Explanation of symbols
S : Start condition
The master device changes the SDA signal from “H” to “L” while the SCL signal is held “H”.
SLA : Slave address
R/W : Indicates the direction of data transmit/receive
Data is transmitted from the slave device to the master device when R/W value is 1 and from the master device to the slave device when
R/W value is 0.
A : Acknowledge
The receive device sets the SDA signal to “L”.
DATA : Transmit / receive data
P : Stop condition
The master device changes the SDA signal from “L” to “H” while the SCL signal is held “H”.
S R/W A DATA A A/A P
1
7
1 1
n
1 1 1
1 m
(a) I
2
C bus format (FS = 0)
Transfer bit numbers (n = 1 to 8)
Transfer frame numbers (m = from 1)
S R/W A
DATA
A/A P
1
7
1 1
n1
1 1
1 m1
(b) I
2
C bus format (when start condition is retransmitted, FS = 0)
Upper: Transfer bit numbers (n1, n2 = 1 to 8)
Lower: Transfer frame numbers (m1, m2 = from 1 )
SLA
SLA
A/A
1
S
1
R/W A
DATA
7
1 1
n2
SLA
1 m2
(1) I
2
C bus Format
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