R8C/20 Group, R8C/21 Group 17. Hardware LIN
Rev.2.00 Aug 27, 2008 Page 350 of 458
REJ09B0250-0200
Figure 17.5 Example of Header Field Transmission Flowchart (1)
Timer RA Set to timer mode
TMOD0 to 2 bits in TRAMR register ← 000b
Timer RA Set the pulse output level from low to start
TEDGSEL bit in TRAIOC register ← 1
Timer RA Set the INT1/TRAIO pin to P1_5
TIOSEL bit in TRAIOC register ← 1
Timer RA Set the count source (f1, f2, f8, fOCO)
TCK0 to 2 bits in TRAMR register
Timer RA Set the Synch Break width
TRAPRE register
TRA register
Hardware LIN Set to master mode
MST bit in LINCR register ← 1
Hardware LIN Set the LIN operation to start
LINE bit in LINCR register ← 1
Hardware LIN Set the register to enable interrupts
(Bus collision detection, Synch Break detection,
Synch Field measurement)
BCIE, SBIE, SFIE bits in LINCR register
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break detection,
Synch Field measurement)
B2CLR, B1CLR, B0CLR bits in LINST register ← 1
Set the count source and the
TRA and TRAPRE registers
as suitable for the Synch
Break period.
During master mode, the
Synch Field measurement-
completed interrupt cannot be
used.
A
Set the TIOSEL bit in the
TRAIOC register to 1 in the
hardware LIN function.
UART0 Set to transmit/receive mode
(Transfer data length: 8 bits, Internal clock, 1 stop bit,
Parity disabled)
U0MR register
UART0 UART0 Set the BRG count source (f1, f8, f32)
U0C0CLK0 to 1 bit
UART0 UART0 Set the bit rate
U0BRG register
Hardware LIN Set the LIN operation to stop
LINE bit in LINCR register ← 0
Set the BRG count source
and U0BRG register as
appropriate for the bit rate.
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