Renesas R8C/20 User Manual

R8C/20 Group, R8C/21 Group 19. Flash Memory
Rev.2.00 Aug 27, 2008 Page 387 of 458
REJ09B0250-0200
Figure 19.6 FMR1 Register
Flash Memory Control Register 1
Symbol Address After Reset
FMR1
01B5h 1000000Xb
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
b3 b2
Set to 0
0
b1 b0
FMR11
—
(b4-b2)
10
b7 b6 b5 b4
RW
FMR15
—
(b0)
Reserved bit
When read, its content is indeterminate.
EW1 mode select bit
(1,2)
0 : EW0 mode
1 : EW1 mode
Block 0 rew rite disable bit
(2,3)
0 : Enables rew rite
1 : Disables rew rite
When the FMR01 bit is set to 1 (CPU rew rite mode enabled), the FMR15 and FMR16 bits can be w ritten.
When setting this bit to 0, set to 0 immediately after setting it first to 1.
When setting this bit to 1, set it to 1.
—
(b7)
0
RW
RW
RW
RO
RW
Reserved bit
0 : Enables rew rite
1 : Disables rew rite
FMR16
Block 1 rew rite disable bit
(2,3)
When setting this bit to 1, set to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1 (CPU rew rite
mode enable) . Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.
This bit is set to 0 by setting the FMR01 bit to 0 (CPU rew rite mode disabled).
Reserved bit Set to 1

Renesas R8C/20 Specifications

General

Brand	Renesas
Model	R8C/20
Category	Control Unit
Language	English