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REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual
0.20 Jun 28, 2006 12 2.8.7 Interrupt Enable Flag (I)
“2.8.7 Interrupt Enable Flag (I Flag)” → “2.8.7 Interrupt Enable Flag (I)”
revised.
2.8.8 Stack Pointer Select Flag (U)
“2.8.8 Stack Pointer Select Flag (U Flag)” → “2.8.8 Stack Pointer
Select Flag (U)” revised.
2.8.10 Reserved Bit
“2.8.10 Reserved Area” → “2.8.10 Reserved Bit” revised.
13 Figure 3.1 Memory Map of R8C/20 Group;
“Internal ROM” → “Internal ROM (program ROM)” revised
Address “1ZZZZh” added.
NOTE revised.
Part Number revised.
14 Figure 3.2 Memory Map of R8C/21 Group;
“Internal ROM” → “Internal ROM (program ROM)” revised.
“Data area” → “Data flash”
“program area” → “program ROM” revised
Address “1ZZZZh” added.
NOTE2 added.
Part Number revised.
15 Table 4.1 SFR Information (1);
001Ch: 00h → 00h, 1000000b
0024h: TBD → Value when shipping
NOTES revised.
24 Figure 5.4 OFS Register, Function of the LVD1ON bit;
“~ after Hardware reset” → “~ after reset” revised.
NOTES revised.
25 5.1.1 When Power Supply is Stable (2) revised.
5.1.2 Power On (4) revised.
26 Figure 5.5 Example of Hardware Reset Circuit and Operation and Figure
5.6 Example of Hardware Reset Circuit (Usage Example of External
Supply Voltage Detection Circuit) and Operation revised.
27 5.2 Power-On Reset Function, on the 2nd line;
“When a capacitor is ~ or more.” added.
Figure 5.7 Example of Power-On Reset Circuit and Operation revised.
NOTES revised.
28 5.3 Voltage Monitor 1 Reset(1); on the 8th line;
The LVD1ON bit in the OFS register can select to~ “after a reset”
added.
29 to 62 “6. Programmable I/O Ports” → “6. Voltage Detection Circuit” and
“7. Voltage Detection Circuit” → “7. Programmable I/O Ports” revised.
32 Figure 6.4 Registers VCA1 and VCA2;
VCA2 register revised.
33 Figure 6.5 VW1C Register revised.
Rev. Date
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