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REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual
0.20 Jun 28, 2006 35 6.1 VCC Input Voltage;
“6.1 Monitoring VCC Input Voltage” → “6.1 VCC Input Voltage”
revised.
42 Figure 7.2 Configuration of Programmable I/O Ports (2) revised.
43 Figure 7.3 Configuration of Programmable I/O Ports (3) revised.
45 Figure 7.5 Configuration of Programmable I/O Ports (5) revised.
47 Figure 7.7 Configuration of Programmable I/O Ports (7) revised.
49 Figure 7.9 PDi (i = 0 to 4 and 6) Registers;
NOTE3 added.
Figure 7.10 Pi (i = 0 to 4 and 6) Registers;
P6 Address “00EEh” → “00ECh” corrected.
51 to 61 7.4 Port Settings added.
63 8.1 Processor Modes
“8.1 Type of Processor Mode” → “8.1 Processor Modes” revised.
64 9. Bus revised;
Table 9.2 Bus Cycles by Access Space of the R8C/21 Group added.
Table 9.3 Access Unit and Bus Operations;
“SFR” → “SFR, data flash”
“ROM/RAM” → “ROM (program ROM), RAM”
below the Table.9.3
“However, only following ~ at a time.” added.
67 Figure 10.2 CM0 Register;
NOTE6 deleted.
69 Figure 10.4 OCD Register;
“System clock select bet(3)” → “System clock select bet(4)”
“1:Selects on-chip oscillator clock(4)” → “1:Selects on-chip oscillator
clock(3)” corrected.
70 Figure 10.5 Registers FRA0 and FRA1;
NOTE2 in the FRA0 register revised.
71 Figure 10.7 VCA2 Register added.
72 Figure 10.8 Examples of XIN Clock Connection Circuit;
NOTE revised.
73 10.2.2 High-Speed On-Chip Oscillator Clock, on the 3rd and 8th lines;
“To use the high-speed ~ (divide-by-4 mode or more).” added.
“Since the difference ~ each bit” → “Since there are ~ individual bits.”
revised.
74 10.3.5 fOCO40M;
“fOCO40M can be used with supply voltage VCC = 3.0 to 5.5V.”
added.
75 Table 10.2 Settings and Modes of Clock Associated Bits;
“-: can be 0 or 1, no change in outcome.” added.
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