SMIQ Digital Modulation
1125.5555.03 E-92.97
2.10.5.2 External Parallel Modulation Data
Parallel data can be fed as symbols via the PAR DATA interface (DATA-D7, -D6 to D0). Either an
external symbol clock (SYMBCLK) or the internal symbol clock can be used. The data at the active edge
of the symbol clock have to be in a stable state. The following figures show the timings at the interface.
In the two examples shown below, the active clock edge is assumed to be positive.
DATA-D7 (input)
SYMBCLK (input)
Fig. 2-57 External parallel data and symbol clock
Data change should take place only on the negative clock edge.
SYMBCLK (output)
DATA-D7 (input)
Internal dataclock
Fig. 2-58 External parallel data and symbol clock
SYMBOL CLOCK = High marks the LSB. A status change of DATA and SYMBOL CLOCK
should be performed synchronously.
External serial modulation data is selected in the menu by SOURCE-SOURCE-EXT_SER.
For modulation types with less than 8 bit/symbol, line DATA-D7 is always the MSB. For QPSK
modulation, for example (2 bit/symbol), data lines DATA-D7 and DATA-D6 are used.
Note: BITCLK pin on the PARDATA interface is an output. Synchronization to an external bit
clock is not possible in this mode.
External parallel modulation data is selected in the menu by SOURCE-SOURCE-EXT_PAR.
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