Rohde & Schwarz SMIQ02B - Table 2-20 Generator Polynomials of Uplink Short Scrambling Code Generators; Table 2-21 Mapping of the Quaternary Output Sequence into the Binary IQ Level

SMIQ Digital Standard 3GPP W-CDMA (FDD)
1125.5555.03 E-92.173
0
7
4
+
mod n addition
c
t
(n)
12356
2
mod 2
07 4
b
s
(n)
12356
2
mod 2
+
mod 4
multiplication
z
v
(n)
07 412356
+
mod 4
Mapper
S
v
(n)
Shift suspend after
every 256-th chip
cycle
a
r
(n)
+ + +
+ ++
+ ++
33
3
2
Fig. 2-99 Structure of the uplink short scrambling code generator
Table 2-20 Generator polynomials of uplink short scrambling code generators
Shift register 1 (binary) x
8
+x
7
+x
5
+x
4
+1
Shift register 2 (binary) x
8
+x
7
+x
5
+x+1
Shift register 3 (quaternary) x
8
+x
5
+3x
3
+x
2
+2x1
The output sequences of the two binary shift registers are weighted with factor 2 and added to the
output sequence of the quaternary shift register (Modulo 4 addition). The resulting quaternary output
sequence is mapped into the binary complex level by the mapper block.
For initialization of the three 8-bit shift registers (in a modified way) the binary form of the 24-bit short SC
number n is used, for details see section 4.3.2.3 in [2].
Table 2-21 Mapping of the quaternary output sequence into the binary IQ level
zv(n) Sv(n)
0+1 + j1
1-1 + j1
2-1 - j1
3+1 - j1
c) Preamble scrambling code generator
When generating the preambles of the PRACH and PCPCH a special SC is used. It is based on the
long SC described under a), however only the I component is taken and subsequently a pointer (e
j(PI/4 +
PI/4 * k)
, k=0 to 4095) modulated upon it.
Modification of the long and short scrambling code output sequence
The scrambling code sequence of the Q component is modified as standard to reduce the crest factor of
the signal. Zero-crossings can then be avoided for every second chip using this method. (This method is
often called HPSK).
For details see [2], section 4.3.2.1. The SMIQ uses a decimation factor of 2.