Bit Error Rate Test SMIQ
1125.5555.03 2.382 E-9
2.23.2.4 Possible BLER Measurement Problems and Solutions
Fault Possible cause Fault description/remedy
BLER
measurement
does not
synchronize
No signals received from
DUT or the signal level is not
correct.
Ø Check activity at BLER measurement inputs in the display.
A status display (Clock, Data, Sync) signals activity on the respective
line.
A wrong clock edge is used,
which violates setup or hold
times.
Ø Check the bit clock signal, the data signal and the DATA ENABLE
signal, if any, on an oscilloscope.
The fault may also be caused by reflections on the clock line, which
clock the data signal twice into the BLER measurement, e.g. if lines are
not terminated. The SMIQ input is not terminated.
Incorrect polarity of data
signal (or DATA ENABLE
signal).
In this case the CRC tester cannot synchronize.
No clock received
from DUT
When testing RF
components, clock recovery
may not be available. An
external clock is however
required for clocking the data
during the BLER
measurement.
The bit clock at the PAR DATA connector of the SMIQ may be used
instead of a clock recovery circuit. This is possible if DGEN (SMIQB11)
is used as a data source. However, this bit clock is not available with all
modulation types. Also, the delay between data and clock has to be
taken into account.
Measured BLER
too high
The data is switched with the
wrong clock edge and/or the
eye pattern of the data is not
optimally met.
Ø Check the clock/data relationship by means of an oscilloscope and
optimize the timing.
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